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1 document # sram111 rev b revised april 2007 features full cmos, 6t cell high speed (equal access and cycle times) ? 10/12/15/20/25/35/45 ns (commercial) ? 12/15/20/25/35 /45 ns (industrial) ? 15/20/25/35/45/55/70/85 ns (military) low power operation ? 743 mw active -10 ? 660/770 mw active for -12/15 ? 550/660 mw active for -20/25 /35 ? 193/220 mw standby (ttl input) ? 83/110 mw standby (cmos input) p4c187 ? 5.5 mw standby (cmos input) p4c187l (military) single 5v10% power supply p4c187/p4c187l ultra high speed 64k x 1 static cmos rams pin configurations functional block diagram dip (p3, d3, c3) lcc pin configurations at end of datasheet. data retention with 2.0v supply (p4c187l military) separate data i/o three-state output ttl compatible output fully ttl compatible inputs standard pinout (jedec approved) ? 22-pin 300 mil dip ? 24-pin 300 mil soj ? 22-pin 290x490 mil lcc ? 28-pin 350x550 mil lcc description the p4c187/p4c187l are 65, 536-bit ultra high speed static rams organized as 64k x 1. the cmos memories require no clocks or refreshing and have equal access and cycle times. the rams operate from a single 5v 10% tolerance power supply. data integrity is maintained for sup- ply voltages down to 2.0v, typically drawing 10a. access times as fast as 10 nanoseconds are available, greatly enhancing system speeds. cmos reduces power consumption to a low 743mw active, 193/83mw standby for ttl/cmos inputs and only 5.5 mw standby for the p4c187l. the p4c187/p4c187l are available in 22-pin 300 mil dip, 24-pin 300 mil soj, 22-pin and 28-pin lcc packages pro- viding excellent board level densities. 1 soj (j4)
p4c187/187l page 2 of 12 document # sram111 rev b maximum ratings (1) symbol parameter value unit v cc power supply pin with ?0.5 to +7 v respect to gnd terminal voltage with ?0.5 to v term respect to gnd v cc +0.5 v (up to 7.0v) t a operating temperature ?55 to +125 c symbol parameter value unit t bias temperature under ?55 to +125 c bias t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w i out dc output current 50 ma recommended operating temperature and supply voltage i sb standby power supply current (ttl input levels) ce v ih mil. v cc = max ., ind./com?l. f = max., outputs open ___ ___ 40 35 ___ ___ ___ ___ 20 15 40 n/a 1.0 n/a ma ma ___ ___ ce v hc mil. v cc = max., ind./com?l. f = 0, outputs open v in v lc or v in v hc standby power supply current (cmos input levels) i sb1 grade(2) ambient temperature gnd v cc 0v 0v 5.0v 10% 5.0v 10% 0v 5.0v 10% ?55c to +125c symbol c in c out parameter input capacitance output capacitance conditions v in = 0v v out = 0v 5 7 unit pf pf capacitances (4) v cc = 5.0v, t a = 25c, f = 1.0mhz n/a = not applicable symbol dc electrical characteristics over recommended operating temperature and supply voltage (2) v ih v il v hc v lc v cd v ol v oh i li i lo parameter input high voltage input low voltage cmos input high voltage cmos input low voltage input clamp diode voltage output low voltage (ttl load) output high voltage (ttl load) input leakage current output leakage current test conditions v cc = min., i in = 18 ma i ol = +8 ma, v cc = min. i oh = ?4 ma, v cc = min. v cc = max. mil. v in = gnd to v cc com?l. v cc = max., ce = v ih , mil. v out = gnd to v cc com?l. p4c187 min 2.2 ?0.5 (3) v cc ?0.2 ?0.5 (3) 2.4 ?10 ?5 ?10 ?5 max v cc +0.5 0.8 v cc +0.5 0.2 ?1.2 0.4 +10 +5 +10 +5 p4c187l min max 2.2 ?0.5 (3) v cc ?0.2 ?0.5 (3) 2.4 ?5 n/a ?5 n/a v cc +0.5 0.8 v cc +0.5 0.2 0.4 ?1.2 +5 n/a +5 n/a unit v v v v v v v a a notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. transient inputs with v il and i il not more negative than ?3.0v and ?100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. typ. military industrial ?40c to +85c 0c to +70c commercial
p4c187/187l page 3 of 12 document # sram111 rev b *v cc = 5.5v. tested with outputs open. f = max. switching inputs are 0v and 3v. ce = v il . data retention characteristics (p4c187l military temperature only) symbol v dr i ccdr t cdr t r ? parameter v cc for data retention data retention current chip deselect to data retention time operation recovery time test conditons ce v cc ?0.2v, v in v cc ?0.2v or v in 0.2v min 2.0 0 t rc typ.* v cc = 2.0v 3.0v max v cc = 2.0v 3.0v unit 10 15 600 900 v a ns ns *t a = +25c t rc = read cycle time ? this parameter is guaranteed but not tested. data retention waveform i cc symbol parameter temperature range dynamic operating current* commercial industrial military ?10 n/a ?12 ?15 ?20 ?25 ?35 ?45 unit n/a ma ma ma power dissipation characteristics vs. speed n/a 150 155 160 170 180 n/a 170 160 155 150 145 180 170 160 155 150 n/a n/a ?85 n/a 145 n/a ?70 n/a 145 n/a ?55 n/a 145 n/a
p4c187/187l page 4 of 12 document # sram111 rev b notes: 5. ce is low and we is high for read cycle. 6. we is high, and address must be valid prior to or coincident with ce transition low. 7. transition is measured 200mv from steady state voltage prior to change with specified loading in figure 1. this parameter is sampled and not 100% tested. 8. read cycle time is measured from the last valid address to the first transitioning address. timing waveform of read cycle no. 2 (6) timing waveform of read cycle no. 1 (5) ac characteristics?read cycle (v cc = 5v 10%, all temperature ranges) (2) minmaxminmaxminmaxminmaxminmaxminmaxminmaxminmaxminmaxminmax t rc read cycle time 10 12 15 20 25 35 45 55 70 85 t aa address access time 10 12 15 20 25 35 45 55 70 85 t ac chip enable access time 10 12 15 20 25 35 45 65 70 85 t oh output hold from address change 2222222222 t lz chip enable to output in low z2222222222 t hz chip disable to output in high z 5 6 8 10 12 17 20 25 30 35 t pu chip enable to power up time0000000000 t pd chip disable to power down time 10 12 15 20 25 35 45 55 70 85 parameter symbol -10 -12 -45 -55 -70 -85 -15 -20 -25 -35
p4c187/187l page 5 of 12 document # sram111 rev b notes: 9. ce and we must be low for write cycle. 10. if ce goes high simultaneously with we high, the output remains in a high impedance state. 11. write cycle time is measured from the last valid address to the first transition address. timing waveform of write cycle no. 1 ( we we we we we controlled) (9) ac characteristics - write cycle (v cc = 5v 10%, all temperature ranges) (2) min max min max min max min max min max min max min max min max min max min max t wc write cycle time 10 12 15 20 25 35 45 55 70 85 t cw chip enable time to end of write 8 101215202530354045 t aw address valid to end of write 8 101215202530354045 t as address set-up time0000000000 t wp write pulse width 8 10 12 15 20 25 30 35 40 45 t ah address hold time from end of write 0000000000 t dw data valid to end of write 6 7 10 13 15 20 25 30 35 40 t dh data hold time0000000000 t wz write enable to output in high z 6 7 8 12 15 17 20 25 30 35 t ow output active from end of write 0000000000 -15-20-25-35-45-55-70-85 parameter symbol -10 -12
p4c187/187l page 6 of 12 document # sram111 rev b timing waveform of write cycle no. 2 ( ce ce ce ce ce controlled) (9) figure 1. output load figure 2. thevenin equivalent * including scope and test fixture. note: due to the ultra-high speed of the p4c187/l, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fingers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal reflections, proper termination must be used; for example, a 50 ? test environment should be terminated into a 50 ? load with 1.73v (thevenin voltage) at the comparator input, and a 116 ? resistor must be used in series with d out to match 166 ? (thevenin resistance). ac test conditions truth table input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 mode ce ce ce ce ce we we we we we output power standby h x high z standby read l h d out active write l l high z active
p4c187/187l page 7 of 12 document # sram111 rev b 28-pin lcc (l5) lcc pin configurations 22-pin lcc (l3)
p4c187/187l page 8 of 12 document # sram111 rev b ordering information selection guide the p4c187 is available in the following temperature, speed and package options. the p4c187l is only available over the military temperature range. * military temperature range with mil-std-883, class b processing. n/a = not available 10 12 15 20 25 35 45 55 70 85 plastic dip -10pc -12pc -15pc -20pc -25pc -35pc -45pc n/a n/a n/a plastic soj -10jc -12jc -15jc -20jc -25jc -35jc -45jc n/a n/a n/a industrial plastic dip n/a -12pi -15pi -20pi -25pi -35pi -45pi n/a n/a n/a plastic soj n/a -12ji -15ji -20ji -25ji -35ji -45ji n/a n/a n/a side brazed dip n/a n/a -15cm -20cm -25cm -35cm -45cm -55cm -70cm -85cm cerdip n/a n/a -15dm -20dm -25dm -35dm -45dm -55dm -70dm -85dm lcc (28 pin) n/a n/a -15l28m -20l28m -25l28m -35l28m -45l28m -55l28m -70l28m -85l28m lcc (22 pin) n/a n/a -15lm -20lm -25lm -35lm -45lm -55lm -70lm -85lm side brazed dip n/a n/a -15cmb -20cmb -25cmb -35cmb -45cmb -55cmb -70cmb -85cmb cerdip n/a n/a -15dmb -20dmb -25dmb -35dmb -45dmb -55dmb -70dmb -85dmb lcc (28 pin) n/a n/a -15l28mb -20l28mb -25l28mb -35l28mb -45l28mb -55l28mb -70l28mb -85l28mb lcc (22 pin) n/a n/a -15lmb -20lmb -25lmb -35lmb -45lmb -55lmb -70lmb -85lmb speed (ns) military temperature military processed* temperature range package commercial
p4c187/187l page 9 of 12 document # sram111 rev b pkg # # pins symbol min max a - 0.225 b 0.015 0.020 b2 0.045 0.065 c 0.009 0.012 d 1.060 1.110 e 0.290 0.320 ea e l 0.125 0.200 q 0.015 0.060 s1 0.005 - 0 15 d3 22 (300 mil) 0.300 bsc 0.100 bsc cerdip dual in-line package side brazed dual in-line packages pkg # # pins symbol min max a 0.100 0.200 b 0.014 0.023 b2 0.030 0.060 c 0.008 0.015 d 1.050 1.260 e 0.260 0.310 ea e l 0.125 0.200 q 0.015 0.070 s1 0.005 - s2 0.005 - c3 22 (300 mil) 0.300 bsc 0.100 bsc
p4c187/187l page 10 of 12 document # sram111 rev b pkg # # pins symbol min max a 0.060 0.080 a1 0.050 0.068 b1 0.022 0.028 d 0.284 0.296 d1 d2 d3 - 0.296 e 0.484 0.496 e1 e2 e3 - 0.496 e h j l 0.039 0.051 l1 0.039 0.051 l1 0.058 0.072 nd ne r = .012 4 7 0.300 bsc 0.150 bsc 0.050 bsc r = .012 l3 22 0.150 bsc 0.075 bsc rectangular leadless chip carrier pkg # # pins symbol min max a 0.128 0.148 a1 0.082 - b 0.016 0.020 c 0.007 0.010 d 0.620 0.630 e e e1 0.292 0.300 e2 q0.025- j4 24 (300 mil) 0.050 bsc 0.267 bsc 0.335 bsc soj small outline ic package
p4c187/187l page 11 of 12 document # sram111 rev b pkg # # pins symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.342 0.358 d1 d2 d3 - 0.358 e 0.540 0.560 e1 e2 e3 - 0.558 e h j l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd ne 0.020 ref 5 9 0.400 bsc 0.200 bsc 0.050 bsc 0.040 ref l5 28 0.200 bsc 0.100 bsc rectangular leadless chip carrier pkg # # pins symbol min max a - 0.210 a1 0.015 - b 0.014 0.022 b2 0.045 0.070 c 0.008 0.014 d 1.145 1.165 e1 0.240 0.280 e 0.300 0.325 e eb - 0.430 l 0.115 0.150 0 15 0.100 bsc p3 22 (300 mil) plastic dual in-line package
p4c187/187l page 12 of 12 document # sram111 rev b revisions document number : sram111 document title : p4c187 / p4c187l ultra high speed 64k x 1 static cmos rams rev. issue date orig. of change description of change or 1997 dab new data sheet a oct-05 jdb change logo to pyramid b apr-07 jdb added 55, 70, and 85 ns speeds

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